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preliminary R7732 1 R7732-04p apr 2010 general description R7732 series is the successor of r7730/1 and fullycompatible with most of sot -23-6 product so far in the market. it's an enhanced, high-performance and currentmode pwm controller . it focuses on "easy to design" in different applications and it will save both design effort andexternal components. besides the general features shown in the features section, R7732 covers wide protection options, such as internal over load protection(olp) and over v oltage protection(ovp) to eliminate the external protectioncircuits. moreover , it also features secondary rectifier short protection (srsp) and cs pin open protection. this protection will make the psu design for reliability and safetyeasier . R7732 is designed for power supply such as nb adaptorwhich is a very cost effective and compact design. the precise external ovp and over t emperature protection (otp) can be implemented by very simple circuit. thestart-up resistors can also be replaced by bleeding resistors to save power loss and component count. enhanced quadruple mode pwm flyback controller features l l l l l uvlo 9v/ 14v l l l l l soft start function l l l l l current mode control l l l l l built-in slope compensation l l l l l internal leading edge blanking l l l l l pwm quadruple mode for green-mode l l l l l excellent green power performance l l l l l cycle-by-cycle current limit l l l l l internal over v oltage protection l l l l l internal over load protection l l l l l secondary rectifier short protection l l l l l opto-coupler short protection l l l l l feedback open-loop protection l l l l l cs pin open protection l l l l l built-in jittering frequency l l l l l built-in pro pin for external arbitrary ovp/otp l l l l l soft driving for emi noise l l l l l high noise immunity l l l l l rohs compliant and halogen free application l l l l l switching ac/dc adaptor and battery charger l l l l l printer power supply l l l l l dvd open frame power supply l l l l l set-t op box (stb) l l l l l a tx standby power l l l l l tv/monitor standby power l l l l l pc peripherals l l l l l nb adaptor pin configurations (top view) sot -23-6 gnd comp pro cs vdd gate 4 2 3 5 6 R7732 v ersion t able version R7732g R7732r R7732l R7732a R7732h frequency 65khz 65khz 65khz 65khz 100khz olp delay time 56ms 56ms 56ms 28ms 36ms internal ovp(27v) auto recovery auto recovery latch latch auto recovery olp & srsp auto recovery auto recovery auto recovery latch auto recovery pro pin high latch auto recovery latch latch auto recovery pro pin low auto recovery latch latch latch latch
preliminary R7732 2 R7732-04p apr 2010 pin no. pin name pin description 1 gnd ground. 2 comp voltage feedback pin. by connecting an opto coupler to close control loop and achieve the regulation. 3 pro for external arbitrary ovp or otp. 4 cs primary current sense pin. 5 vdd power supply pin. 6 gate gate drive output to drive the external mosf et. pin description t ypical application circuit ac mains (9 0v to 265v) pro comp gnd gate cs R7732 vdd + + vo+ vo 5 6 2 1 4 # # see application information 3 ntc ordering information note : richpower green products are : } rohs compliant and compatible with the current requirements of ipc/jedec j-std-020. } suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richpower distributor located in yourarea, otherwise visit our website for detail. R7732 package type e : sot236 operating temperature range g : green (halogen free with commercial standard) R7732 version (refer to version table)
preliminary R7732 3 R7732-04p apr 2010 block diagram counter vdd (5) gate (6) leb r s q ss x3 slope ramp v comp v burh v burl pwm comparator shutdown logic comp open sensing brownout sensing dmax oscillator por 27v bias & bandgap uvlo ovp 9v/14v olp constant power soft driver +- +- + - - + - 1.7v secondary rectifier short & cs open protection comp (2) cs (4) pro (3) quadruple mode + - + - latch v l_th v h_th gnd (1) v dd i bias auto recovery latch auto recovery
preliminary R7732 4 R7732-04p apr 2010 electrical characteristics parameter symbol conditions min typ max unit vdd section v dd over voltage protection level v ovp 26 27 28 v v dd zener clamp v z 29 v on threshold voltage v th_on 13 14 15 v off threshold voltage v th_off 8.5 9 9.5 v vdd holdup mode entry point v dd_low v comp <1.6v 10 v vdd holdup mode ending point v dd_high v comp <1.6v 10.5 v startup current i dd_st v dd = v th_on C 0.2v, t a = 40oc to 100oc 20 35 a operating supply current i dd_op v dd = 15v, v comp = 2.5v, gate pin open 1.3 2.2 ma latchoff operating current i dd_lh t a = 40oc to 100oc 40 a t o be continued recommended operating conditions (note 4) l supply input v oltage, v dd ----------------------------------------------------------------------------------------- 12v to 25v l ambient t emperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) l supply input v oltage, v dd ----------------------------------------------------------------------------------------- ? 0.3v to 30v l ga te pin -------------------------------------------------------------------------------------------------------------- ? 0.3v to 16.5v l pro, comp , cs pin ----------------------------------------------------------------------------------------------- ? 0.3v to 6.5v l i dd ----------------------------------------------------------------------------------------------------------------------- 10ma l power dissipation, p d @ t a = 25 c sot -23-6 -------------------------------------------------------------------------------------------------------------- 0.4w l package thermal resistance (note 2) sot -23-6, ja -------------------------------------------------------------------------------------------------------- 250 c/w l junction t emperature ----------------------------------------------------------------------------------------------- 150 c l lead t emperature (soldering, 10 sec.) ------------------------------------------------------------------------- 260 c l storage t emperature range --------------------------------------------------------------------------------------- ? 65 c to 150 c l esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------- 3kv mm (machine mode) ------------------------------------------------------------------------------------------------ 250v (v dd = 15v , t a = 25 c, unless otherwise specified)
preliminary R7732 5 R7732-04p apr 2010 parameter symbol conditions min typ max unit oscillator section R7732g/r/l/a 60 65 70 normal pwm frequency f osc R7732h 92 100 108 khz R7732g/r/l/a 18 22 frequency reduction mode minimum frequency f fr_min R7732h 25 khz maximum duty cycle dcy max 70 75 80 % pwm frequency jitter range f 6 % pwm frequency jitter period t jit for 65khz 4 ms frequency variation versus v dd deviation f d v v dd = 12v to 25v 2 % frequency variation versus temperature deviation f d t t a = 30c to 105c (note 5) 5 % comp input section openloop voltage v comp_op comp pin open 5.5 5.75 6 v R7732g/r/l 56 R7732a 28 comp openloop protection delay time t olp R7732h 36 ms short circuit current i zero v comp = 0v 1.2 2.2 ma frequency reduction mode entry voltage v fr_et 3 v R7732g/r/l/a 2.9 frequency reduction mode ending voltage v fr_ed R7732h 2.8 v current-sense section initial peak current limitation offset v cs_th 0.68 0.7 0.72 v leading edge blanking time t leb (note 6) 150 250 350 ns internal propagation delay time t pd (note 6) 100 ns minimum on time t on_min 250 350 450 ns gate section rising time t r v dd = 15v, c l = 1nf 125 ns falling time t f v dd = 15v, c l = 1nf 40 ns gate output clamping voltage v clamp v dd = 25v 14 v t o be continued
preliminary R7732 6 R7732-04p apr 2010 note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only , and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability . note 2. ja is measured in the natural convection at t a = 25 c on a low ef fective single layer thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. note 6. leading edge blanking time and internal propagation delay time are guaranteed by design. note 7. the sourcing current of pro pin must be limited below 5ma. otherwise it may cause permanent damage to the device. parameter symbol conditions min typ max unit pro interface section pull low threshold v l_th 0.47 0.5 0.53 v pull high threshold v h_th 3.5 3.8 4.1 v internal bias current i bias 90 100 110 a pull high sinking current i sink (note 7) 1.2 ma
preliminary R7732 7 R7732-04p apr 2010 t ypical operating characteristics start-up current (i dd_st ) vs. v dd 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 v dd (v) i dd_st (a) t a = 25 c normal pwm frequency (f osc ) vs. v dd 63 64 65 66 67 10 15 20 25 v dd (v) f osc (khz) R7732g/r/l/a normal pwm frequency (f osc ) vs. temperature 60 62 64 66 68 40 0 40 80 120 temperature f osc (khz) ( c) R7732g/r/l/a normal pwm frequency (f osc ) vs. temperature 94 96 98 100 102 104 40 0 40 80 120 temperature f osc (khz) ( c) R7732h normal pwm frequency (f osc ) vs. v dd 96 98 100 102 104 10 15 20 25 v dd (v) f osc (khz) R7732h start-up current (i dd_st ) vs. temperature 10 15 20 25 30 40 0 40 80 120 temperature i dd_st (a) ( c)
preliminary R7732 8 R7732-04p apr 2010 frequency reduction mode minimum frequency (f fr_min ) vs. temperature 10 15 20 25 30 40 0 40 80 120 temperature f fr_min (khz) ( c) comp open-loop voltage (v comp_op ) vs. temperature 5.2 5.4 5.6 5.8 6 40 0 40 80 120 temperature v comp_op (v) ( c) v dd over voltage protection (v ovp ) vs. temperature 25 26 27 28 29 40 0 40 80 120 temperature v ovp (v) ( c) operating supply current (i dd_op ) vs. temperature 1.0 1.2 1.4 1.6 1.8 40 0 40 80 120 temperature i dd_op (ma) ( c) v dd = 15v , v comp = 2.5v , ga te pin open on threshold voltage (v th_on ) vs. temperature 12 13 14 15 16 40 0 40 80 120 temperature v th_on (v) ( c) off threshold voltage (v th_off ) vs. temperature 8.0 8.5 9.0 9.5 10.0 40 0 40 80 120 temperature v th_off (v) ( c)
preliminary R7732 9 R7732-04p apr 2010 pro pin internal bias current (i bias ) vs. temperature 70 80 90 100 110 40 0 40 80 120 temperature i bias (a) ( c) initial peak current limitation offset (v cs_th ) vs. temperature 0.60 0.65 0.70 0.75 0.80 40 0 40 80 120 temperature v cs_th (v) ( c) olp delay time (t olp ) vs. temperature 20 25 30 35 40 40 0 40 80 120 temperature t olp (ms) ( c) R7732a olp delay time (t olp ) vs. temperature 25 30 35 40 45 40 0 40 80 120 temperature t olp (ms) ( c) R7732h olp delay time (t olp ) vs. temperature 50 55 60 65 70 40 0 40 80 120 temperature t olp (ms) ( c) R7732g/r/l latch-off operating current (i dd_lh ) vs. temperature 10 15 20 25 30 35 40 40 0 40 80 120 temperature i dd_lh (a) ( c)
preliminary R7732 10 R7732-04p apr 2010 falling time (t f ) vs. temperature 20 30 40 50 60 40 0 40 80 120 temperature t f (ns) ( c) rising time (t r ) vs. temperature 100 110 120 130 140 40 0 40 80 120 temperature t r (ns) ( c) gate clamping voltage (v clamp ) vs. temperature 10 12 14 16 18 40 0 40 80 120 temperature v clamp (v) ( c) maximum duty cycle (dcy max ) vs. temperature 70 72 74 76 78 40 0 40 80 120 temperature dcy max (%) ( c) pro pin pull high threshold (v h_th ) vs. temperature 2 3 4 5 6 40 0 40 80 120 temperature v h_th (v) ( c) pro pin pull low threshold (v l_th ) vs. temperature 0.40 0.45 0.50 0.55 0.60 40 0 40 80 120 temperature v l_th (v) ( c)
preliminary R7732 11 R7732-04p apr 2010 ? burst mode : during light load, switching loss will dominate the power efficiency calculation. this modeis to cut switching loss. as shown in figure 1, when the output load gets light, feedback signal drops andtouches v burl . pwm signal will be blanked and system ceases to switch. after v out drops and feedback signal goes back to v burh , switching will be resumed. application information pwm quadruple mode R7732 applies quadruple mode for improving efficiency atlight load operation. please also refer to figure 1 for details. ? pwm mode : for most of load, the circuit will run at traditional pwm current mode. # it's highly recommended to add a resistor in parallel with opto-coupler . t o provide suf ficient bias current to make tl-431 regulate properly , 1.2k resistor is suggested. ? frequency reduction mode : the frequency reduction mode function provides linear switching frequencyreduction according to load conditions, as shown in figure 2. when the feedback voltage of comp pin is lower than v fr_et , the switching frequency starts to decrease. when the power supply is at light-load and the feedback voltage of comp pin lower than v fr_ed , the switching frequency is clamped at f fr_min . thi s frequency reduction mode function reduces powerconsumption under light-load and no-load conditions, and easily meets even the strictest regulations. f osc f fr _min v fr_et freq. v comp v fr_ed load v dd v dd_high v dd_low normal operation frequency reduction mode burst mode vdd holdup mode v comp v burh v burl gate figure 2. pwm frequency vs. comp v oltage figure 1. pwm quadruple mode
preliminary R7732 12 R7732-04p apr 2010 figure 3. i dd_avg vs. r bleeding curve light load or no load condition, normally . start-up circuit t o minimize power loss, it's recommended that the start- up current is from bleeding resistor . it's not only good for power saving but also could reset latch mode protection quickly . figure 3 shows i dd_a vg vs. r bleeding curve. user can apply this curve to design the adequate bleeding resistor . gate driver a totem pole gate driver is fine tuned to meet both emiand ef ficiency requi rement in low power application. an internal pull low circuit is activated after pretty low v dd to prevent external mosfet from accidentally turning onduring uvlo. oscillator t o guarantee precise frequency , it's trimmed to 5% tolerance. it also generates slope compensation saw-tooth,75% maximum duty cycle pulse and overload protection ? vdd holdup mode: under light load or load transient moment, feedback signal will drop and touch v burl . then pwm signal will be blanked and system ceases to switch. v dd could drop down to turn off threshold voltage. t o avoid this, when v dd drops to a setting threshold, 10v , the hysteresis comparator will bypass pwm and burst mode loop and forces switching at a very low level to supply energy to vdd pin. vdd holdupmode was also improved to hold up v dd by less switching cycles. this mode is very useful in reducing start-upresistor loss while still get start-up time in spec. it's not likely for v dd to touch uvlo turn off threshold during any light load condition. this will also makes biaswinding design and transient design easier . furthermore, vdd holdup mode is only designed to prevent v dd from touching turn off threshold voltage under light load or load transient moment. relative to burst mode, switching loss will increase on the system at vdd holdup mode, so it is highly recommended that the system should avoid operating at this mode during r bleeding r bleeding v dd i dd_avg
preliminary R7732 13 R7732-04p apr 2010 soft startduring initial power on, especially at high line, current spike is kind of unlimited by current limit. therefore, besides cycle-by-cycle current limiting, R7732 still provides soft start function. it effectively suppresses the stat-up current spike. the typical soft start duration is about 40 clock cycles. this will provide more reliable operation and possibility to use smaller current rating power mosfet . protection r 7732 provide fruitful protection functions that intend to protect system from being damaged. all the protection functions can be listed as below: ? ? ? ? ? cycle-by-cycle current limit: this is a basic but very useful function and it can be implemented easilyin current mode controller . ? ? ? ? ? over load protection: long time cycle-by-cycle current limit will lead to system thermal stress. t o further protect system, system will be shut down after 56ms ( R7732a: 28ms; R7732h: 36ms ) . through our proprietary prolong turn off period during hiccup(R7732a: latch), the power loss and thermalduring olp will be averaged to an acceptable level over the on/off cycle of the ic. this will last until fault is removed. slope. it can typically operate at built-in 65khz centerfrequency and features frequency jittering function. its jittering depth is 6% with about 4ms envelope frequency at 65khz. t ight current limit t olerance since R7732 is the successor of r7731a, its current limitsetting is completely the same as r7731a. generally , the saw current limit applied to low cost flyback controllerbecause of simple design. however , saw current limit is hard to test in mass production. therefore, it's generally"guaranteed by design". the variation of process and package will make its tolerance wider . it will lead to 20% to 30% variation when doing olp test at certain linevoltage. this will cause yield loss in power supply mass production. through well foundry control, design and test / trim mode in final test, R7732 current limit tolerance is tight enough to make design easier . pro pin application r7 732 features a pro pin, as shown in figure 4, and it can be applied for external arbitrary ovp or otp . if the voltage of pro pin is greater than pull-low threshold v l_th , the controller is enabled and switching will occur . if the voltage of pro pin falls below pull-low threshold or rises to pull-high threshold v h_th , the controller will be shut down and cease to switch after deglitch delay . pro pin is built in 1.5v internally , so leave pro pin open if you don't need this function. if designer needs to applya bypass capacitor on pro pin, it should not be more than 1nf . the internal bias current of pro pin is 100 a(t yp.). R7732 has internal ovp . for arbitrary ovp or otp applications which behave as auto recovery orlatch, it can get these by pro pin. for pro pin pulling high function applications, the voltage of pro pin must rise above v h_th (the supply current of pro pin must be greater than 1.2ma and be limited below 5ma.). when icenters latch mode, the ic maximum operating current is 60 a(100 c) , and it will be release until v dd is fallen to v th_off . pro pin is guaranteed that below: if the voltage of propin reaches 4.1v or falls below 0.47v , the system will be protected. +- +- i bias pro v l_th v h_th deglitch 30s auto recovery v l_th v h_th v pro auto recovery / latch normal operating deglitch 50s latch auto recovery / latch figure 4. pro pin diagram
preliminary R7732 14 R7732-04p apr 2010 ? ? ? ? ? brownout protection: during heavy load, this will trigger 56ms( R7732a: 28ms; R7732h: 36ms ) protection and shut down the system. if it is in light load condition,system will be shut down after v dd is running low and triggers uvlo. ? ? ? ? ? cs pin open protection: when cs pin is opened, the system will be shut down after couples of cycle. itcould pass cs pin open test easier . ? ? ? ? ? over v oltage protection: output voltage can be roughly sensed by vdd pin. if the sensed voltage reaches 27v threshold, system will be shut down and hiccup after 20 s deglitch delay for R7732g/r/h or latch after 70 s deglitch delay for R7732l/a. this will last until fault is removed. ? ? ? ? ? feedback open and opto-coupler short: this will trigger ovp or olp . it depends on which one occurs first. ? ? ? ? ? secondary rectifier short protection: as shown in figure 5. the current spike during secondary rectifier short test is extremely high because of the saturated main transformer . meanwhile, the transformer acts like a leakage inductance. during high line, the current in power mosfet i s sometimes too high to wait for olp delay time. t o of fer better and easier protection design, R7732 shut down the controller after couples of cyclesbefore fuse is blown up. figure 5. secondary rectifier short protection secondary rectifier short v dd v cs v comp R7732g
preliminary R7732 15 R7732-04p apr 2010 vdd v dd ovp : v dd > v r + v z + 3.8v vo+ pro pro ntc ( option) pro (option) (option) (option) vdd pro (option) pro pin t ypical application circuit figure 6. for vdd ovp only figure 7. for otp only figure 8. for vdd ovp figure 9. for v out ovp
preliminary R7732 16 R7732-04p apr 2010 pcb layout guide a proper pcb layout can abate unknown noise interferenceand emi issue in the switching power supply . please refer to the guidelines when you want to de sign pcb layout for switching power supply:i. the current path (1) from bulk capacitor , transformer , mosfet , rcs return to bulk capacitor is a huge high frequency current loop. it must be as short as possibleto decrease noise coupling and kept a space to other low voltage traces, such as ic control circuit paths, especially . ii. the path(2) from rcd snubber circuit to mosfet is also a high switching loop, too. keep it as small aspossible. iii. it is good for reducing noise, output ripple and emi issue to separate ground traces of bulk capacitor(a), ( a ) (d) (b) (1) (c) (2) auxiliary ground (c) ic ground (d) trace trace trace mosfet ground (b) c bulk ground (a) ac mains (90v to 265v) pro comp gnd gate cs R7732 vdd 5 6 2 1 4 3 ntc c bulk mosfet(b), auxiliary winding(c) and ic control circuit(d). finally , connect them together on bulk capacitor ground(a). the areas of these ground traces shouldbe kept large. iv . placing bypass capacitor for abating noise on ic is highly recommended. the bypass capacitor shouldbe placed as close to controller as possible. v . in order to minimize reflected trace inductance and emi, it is minimized the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor . in addition, apply suf ficient copper area at the anode and cathode terminal of the diode for heatsinking. apply a larger area at the quiet cathode terminal. a large anode area can increase high-frequency radiated emi.
preliminary R7732 17 R7732-04p apr 2010 richpower microelectronics corp . t aipei of fice (marketing) 8f , no. 137, lane 235, paochiao road, hsintien city t aipei county , t aiwan, r.o.c. t el: (8862)89191466 fax: (8862)89191465 information that is provided by richpower t echnology corporation is believed to be accurate and reliable. richpower reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringement of the applications should be guaranteed by users when integrating richpower products into any application. no legal responsibility for any said applications is assumed by richpower. richpower microelectronics corp . headquarter room 2102, 1077 zuchongzhi road, zhang jiang hi-t echpark, pudong new area, shanghai, china t el: (8621)50277077 fax: (8621)50276966 outline dimension a a1 e b b d c h l dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.031 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 sot -23-6 surface mount package

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